In a PLL (Phase-Locked Loop) circuit utilized in a circuit for reading a magnetic disk or a circuit for receiving a data transmission or the like, an ICO (current-controlled oscillator) is used in many cases for taking out an output signal synchronous with a desired signal. Usually, a digital signal is output from a phase comparator that is a constituent element of the PLL circuit. Therefore, when the ICO is used, it is particularly necessary to provide a digital-to-analog conversion circuit which converts the digital signal output from the phase comparator into an analog control current.
FIG. 5 shows a circuit structure of a conventional digital-to-analog conversion circuit used in the PLL circuit and others. To facilitate the explanation, the digital-to-analog conversion circuit shown in FIG. 5 has a circuit structure for inputting four-bit digital data. Usually, digital data output from the phase comparator is first stored in registers constituting a buffer, and the ICO converts the data stored in the registers into a current value. Referring to FIG. 5, registers 0 to 3 represent bits of four-bit data stored in these registers. The register 3 has a highest-order bit and the register 0 has a lowest-order bit.
The digital-to-analog conversion circuit shown in FIG. 5 includes inverters G0 to G3 which invert the inputs of the registers 0 to 3 respectively. This digital-to-analog conversion circuit also includes twelve MOS transistors and four inverters for taking out a current from a power source voltage Vdd according to signals output from the inverters G0 to G3 and for outputting the current taken out as a DAC current (a digital-to-analog current). Particularly, a structure having three MOS transistors and one inverter is allocated to each bit stored in each register.
As shown in FIG. 5, a p-channel MOS transistor M12 with its source connected to the power source voltage Vdd and a p-channel MOS transistor M13 with its drain connected to a constant current source 9 are connected in series to the register 0. A p-channel MOS transistor M11 with its source connected to the power source voltage Vdd and with its drain connected to an output terminal of a DAC current has its gate connected to a connection point between the p-channel MOS transistors M12 and M13, that is, the drain of the p-channel MOS transistor M12 and the source of the p-channel MOS transistor M13.
Then, an output of an inverter G10 for further inverting the output. of the inverter G0 is input into the gate of the p-channel MOS transistor M12. The output of the inverter G0 is input into the gate of the p-channel MOS transistor M13. In this case, a channel width (hereinafter to be referred to as a W-size) of the p-channel MOS transistor M11 is set to a.
Based on this structure, when the register 0 has a logic level "L", the output of the inverter G0 will have a logic level "H". This logic level "H" is input into the gate of the p-channel MOS transistor M13, to turn OFF the p-channel MOS transistor M13. Further, as the output of the inverter G0 is input into the inverter G10, the output of the inverter G10 will have a logic level "L". This logic level "L" is input into the gate of the p-channel MOS transistor M12, to turn ON the p-channel MOS transistor M12. Thus, the potential of the gate of the p-channel MOS transistor M11 increases, and the p-channel MOS transistor M11 is turned OFF. Therefore, the electric current is not supplied by the drain of the p-channel MOS transistor M11, and accordingly the DAC current does not increase.
On the other hand, when the register 0 has the logic level "H", the output of the inverter G0 will have a logic level "L". This logic level "L" is input into the gate of the p-channel MOS transistor M13, to turn ON the p-channel MOS transistor M13. Further, the output of the inverter G10 has the logic level "H", and this logic level "H" turn OFF the p-channel MOS transistor M12. Thus, the potential of the gate of the p-channel MOS transistor M11 is lowered by the lead-in current of the constant current source 9, and the p-channel MOS transistor M11 is turned ON. In other words, a current taken out from the power source voltage Vdd appears in the drain of the p-channel MOS transistor M11, and this current is added to the DAC current.
Similarly, a p-channel MOS transistor M22 having its source connected to the power source voltage Vdd and a p-channel MOS transistor M23 having its drain connected to a constant current source 9 are connected in series to the register 1. A p-channel MOS transistor M21 with its source connected to the power source voltage Vdd and with its drain connected to an output terminal of a DAC current has its gate connected to a node between the p-channel MOS transistors M22 and M23, that is, the drain of the p-channel MOS transistor M22 and the source of the p-channel MOS transistor M23.
Output of an inverter G20 which inverts the output of the inverter G1 is input into the gate of the p-channel MOS transistor M22. The output of the inverter G1 is input into the gate of the p-channel MOS transistor M23. The W-size of the p-channel MOS transistor M21 is set to two times the W-size of the p-channel MOS transistor M11, that is a.times.2. Since the drain current of the MOS transistor is directly proportional to the W-size, the drain current of the p-channel MOS transistor M21, that is the current that can be added to the DAC current, becomes two times the drain current of the p-channel MOS transistor M11.
With such a constitution, when the register 1 has the logic level "L", the output of the inverter G1 will have a logic level "H". This logic level "H" turns OFF the p-channel MOS transistor M23. As the output of the inverter G1 is input into the inverter G20, the output of the inverter G20 will have a logic level "L". This logic level "L" turns ON the p-channel MOS transistor M22. Thus, the gate potential of the p-channel MOS transistor M21 is increased, and the p-channel MOS transistor M21 is turned OFF. Therefore, the electric current is not supplied by the drain of the p-channel MOS transistor M21, and accordingly the DAC current does not increase.
On the other hand, when the register 0 has the logic level "H", the output of the inverter G1 will have a logic level "L". This logic level "L" turns ON the p-channel MOS transistor M23. Further, the output of the inverter G20 has the logic level "H", and this logic level "H" turns OFF the p-channel MOS transistor M22. Thus, the potential of the gate of the p-channel MOS transistor M21 is lowered by the lead-in current of the constant current source S, and the p-channel MOS transistor M21 is turned ON. In other words, a current taken out from the power source voltage Vdd appears in the drain of the p-channel MOS transistor M21, and this current is added to the DAC current.
The register 2 and the register 3 also have structures and operations similar to those described above, and their explanation will be omitted. However, in FIG. 5, of the structure corresponding to the register 2, the W-size of a p-channel MOS transistor M31 is four times the W-size of the p-channel MOS transistor M11, that is a.times.4. Further, of the structure corresponding to the register 3, the W-size of a p-channel MOS transistor M41 is eight times the W-size of the p-channel MOS transistor M11, that is a.times.8. Accordingly, the drain currents of the p-channel MOS transistors M31 and M41 also are four times and eight times of the drain current of the p-channel MOS transistor M11 respectively.
As explained above, there is provided for each of the registers 0 to 3 a structure for adding a current to the DAC current according to the signal level of each register. Further, the W-sizes is changed among the MOS transistors M11, M21, M31 and M41 that supply a current respectively. With this arrangement, it is possible to output the DAC current as a sum of signals of these registers, that is, as a sum of currents of these registers with different weight on each bit. In the drawing, a p-channel MOS transistor M0 functions as a load element. In this case, the W-size of this transistor M0 is ten times the W-size of the p-channel MOS transistor M11, that is, a.times.10.
FIG. 6A and FIG. 6B are diagrams which show an example of DAC current values that are output based on the values of the resisters 0 to 3 in the prior-art digital-to-analog conversion circuit (current value of the constant current source 9 is 100 .mu.A). For example, as shown in FIG. 6A, when the register 3, the register 2, the register 1 and the register 0 have the logic levels "H", "H", "L" and "H" respectively, that is, when the four-bit data is "1101", a DAC current of 130 .mu.A is output as a result of the sum of the drain currents of the p-channel MOS transistors M41, M31 and M11, that is, the sum of 80 .mu.A, 40 .mu.A and 10 .mu.A.
In other words, as a decimal value expressed by the four bits of the registers 0 to 3 increases from 0 to 15, the DAC current value increases linearly as shown in FIG. 6B. Accordingly, in the PLL circuit, each time when a digital value output from the phase comparator increases by one, a DAC current that increases linearly is input into the ICO.
In general, the above-described ICO is for increasing the oscillation frequency of the signal that is output based on the increase in the input current value. However, as the oscillation frequency to be obtained becomes higher, the increase in the oscillation frequency obtained for each increase in the current value becomes smaller. Thus, the characteristics of the oscillation frequency become non-linear as the oscillation frequency to be obtained becomes higher.
In the above-described conventional digital-to-analog conversion circuit, the DAC current value increases linearly along with an increase in the input digital value (DAC register value). However, when this DAC current value is input into the ICO, the angle of the slope of increase in the oscillation frequency of the signal output from the ICO becomes smaller as the digital value output from the phase comparator attains a larger value. Therefore, there is a problem that a high-speed synchronization can not be carried out when signals of a large phase difference are input into the PLL circuit.
FIG. 7 is a diagram which shows the above-described relationship between the DAC register values and the oscillation frequency in the PLL circuit. As shown in FIG. 7, when a linear relationship between the DAC register values and the DAC current values in the conventional digital-to-analog conversion circuit is added to a non-linear relationship between the DAC current values and the oscillation frequency in the ICO, there is obtained a non-linear relationship between the DAC register values and the oscillation frequency.